The present invention relates in general to semiconductor power field effect transistors (FETs) and in particular to shielded gate power FETs with self aligned features.
The vertical trench gate MOSFET has been widely used in power devices for its superior performance characteristics including high speed and low on resistance, RDSon. The RDSon can be further reduced by increasing the trench density. This may be achieved by shrinking the cell pitch or the size of devices, to enable more MOSFETs to be formed per square area of silicon. The cell pitch is determined by the width of the trench, source and body regions.
However, reducing the cell pitch is limited by manufacturing and design limitations because features cannot generally be made smaller than the resolution of photolithography tools. Changing the lithography design is a costly approach to reducing the cell pitch. Moreover, misalignment tolerances in the masking steps for forming the source and heavy body regions have hindered the cell pitch reduction efforts. While some techniques for achieving self-aligned features in FETs have been disclosed, these techniques typically require more process steps and increased process complexity, and thus are not cost-effective techniques.
Thus, there is a need for improved FETs and methods of forming the same.